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BAR Parameters
CorePCIF supports up to six BARs and the Expansion ROM address register. Enabling all the BARs will have a
significant effect on logic utilization. For the SX-A and RTSX-S families, only BAR 0 and BAR 1 can be used to access
backend memory. BAR 2 can be used to access the DMA registers. BARs 3 to 5 and the Expansion ROM are not
supported in the SX-A and RTSX-S families. Table 4-3 displays BAR parameters. The variable i can have a value from
0 to 5.
Table 4-3 · BAR Parameters
Name
BAR i _ENABLE
BAR i _ADDR_WIDTH
BAR i _IS_IO
BAR i _PREFETCH
BAR i _64BIT
BAR i _INITVAL
EXPR_ENABLE
EXPR_ADDR_WIDTH
EXPR_64BIT
38
Values
0 to 2
4 to 32
0 or 1
0 or 1
0 or 1
0 to
268,435,455
0 to 1
4 to 32
0 or 1
Description
0: BAR i is disabled.
1: BAR i is enabled without FIFO recovery.
2: BAR i is enabled with FIFO recovery.
Specifies the width of the BAR. A value of 8 would create a 256-byte address space.
If the BAR is disabled, this should be set to 4.
BAR_SIZE = 2 BAR i _ADDR_WIDTH
0: BAR i is configured as memory space.
1: BAR i is configured as I/O space.
If BAR i is memory space, this bit controls the PREFETCH bit in the BAR.
0: Prefetch is disabled for BAR i .
1: Prefetch is enabled for BAR i .
This should be set to zero when the FIFO recovery logic is enabled.
0: BAR i supports only 32-bit transfers.
1: BAR i supports 32- and 64-bit transfers (PCI_WIDTH must also be set to 64).
Specifies the reset value of the upper 28 bits of the BAR at reset. For PCI compliance, this
should be set to zero. If non-zero, BAR i _INITVAL allows the core to respond to PCI
accesses without the BAR being programmed. If the BAR initialization value is required to
be 0x80001000, the parameter should be set to the required value divided by 16 (that is,
0x08000100).
The division is required because the value provided is used to set the upper 28 bits. The
lowest 4 bits are set depending on the BAR i _IS_IO and BAR i _PREFETCH values.
0: Expansion ROM is disabled.
1: Expansion ROM is enabled.
Specifies the width of the Expansion ROM register. A value of 8 would create a 256-byte
address space.
If the Expansion ROM is disabled, this should be set to 4.
0: Expansion ROM supports only 32-bit transfers.
1: Expansion ROM supports 32- and 64-bit transfers (PCI_WIDTH must also be set to
64).
v4.0
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